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What Changed
Reject missing Liberty cell models during iSTA initialization, before building the timing graph. Previously, an omitted SRAM library caused the graph builder to substitute generic input-to-output connectivity. SRAM clocks could then enter data logic, disable global path-state pruning, and cause propagation memory to grow until the process was killed.
The reader now checks imported non-port signal pins against the current Liberty generation. The error identifies missing cell types, instance counts, and an example instance, and asks the caller to load the matching corner and macro libraries. Physical-only instances without signal pins remain accepted.
The regression covers missing SRAM models, physical-only cells, successful loading with SRAM timing arcs, and a later corner reload that drops the SRAM library. CPPR formulas and pruning thresholds are unchanged. This PR contains four source/test/build files and no documentation files.
Scope
Runtime And Packaging Impact
Initialization now fails explicitly for every imported signal-bearing cell without a Liberty model, including constraint-only initialization. The existing Tcl/Python error paths propagate that failure. No public API signature, dependency, toolchain, or packaging change; CMake only registers the regression test.
Validation
--dry-run --Werroron all three changed C++ files;git diff --checkpassed.cmake --build build/release --target test_ista_missing_liberty test_ista_read_network test_ista_interface test_ista_clock_check_reader test_ista_retaining_arc -j 4.ctest --test-dir build/release --output-on-failure -R '^ista_(missing_liberty|read_network|interface|clock_check_reader|retaining_arc)$'— 5/5 passed.The reported
ysyx_050228_memMAX_125_Cworst scenario omitted the Liberty model for 32 SRAM instances. With the original incomplete configuration, the patched binary reports the missing model and exits before graph propagation. With the matching SRAM library added to the original DEF/SDC/Cworst SPEF inputs, the full run completes in 4m14.51s with peak RSS 38.34 GiB. With those complete inputs, all 21 timing/electrical report files match before/after this patch byte-for-byte; SDF matches after excluding its date field. The improvement requires correcting the scenario library list; the guard does not supply missing timing models or change CPPR pruning.The earlier wider local run passed 122/124 tests. The two failures (
ista_read_config,ista_driver_response) relate to pre-existing, uncommitted configuration/delay-calculator changes and neither executable linksista_reader. Those changes are not in this PR. The scenario measurements were also taken in that worktree with those unrelated changes held fixed before/after; they are not a clean-checkout CI result.Checklist
uv.lockor version metadata when dependencies changed: N/A.