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hemanshuEng
FPGA
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About
FPGA - VHDL
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fpga
vhdl
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001.test
001.test
002.ORgate
002.ORgate
003.or_gate_4bit
003.or_gate_4bit
004.or_gate_4bit_for_loop
004.or_gate_4bit_for_loop
005.And_gate
005.And_gate
006.and_gate_nbit
006.and_gate_nbit
007.Inverter
007.Inverter
008.inverter_nbit
008.inverter_nbit
009.XOR_gate
009.XOR_gate
010.XOR_gate_nbit
010.XOR_gate_nbit
011.2to1Mux_if_statement
011.2to1Mux_if_statement
012.4to1Mux
012.4to1Mux
013.Generic MUX
013.Generic MUX
015.7segment_decoder using case statement
015.7segment_decoder using case statement
016.Multiplexing 7segment display
016.Multiplexing 7segment display
017.7segment display using clock
017.7segment display using clock
018.clkdiv
018.clkdiv
019.binarytograycode
019.binarytograycode
020.binarytobcd
020.binarytobcd
021.4bitCompartor
021.4bitCompartor
022.Nbitcompartor
022.Nbitcompartor
023.Decoder38
023.Decoder38
024.Encoder
024.Encoder
025.HalfAdder
025.HalfAdder
026.fulladder
026.fulladder
027.fulladder4bitlogic
027.fulladder4bitlogic
028.fulladder4bitBehavioral
028.fulladder4bitBehavioral
029.fulladderNbit
029.fulladderNbit
030.addersubtractor
030.addersubtractor
031.subtractorBehavioral
031.subtractorBehavioral
034.Multiplier
034.Multiplier
035.Multiplier using library
035.Multiplier using library
040.D Flip-Flops with clear and set
040.D Flip-Flops with clear and set
041.divider2counterusingDF
041.divider2counterusingDF
042.1BitRegister
042.1BitRegister
043.Register4bit
043.Register4bit
044.RegisterNbit
044.RegisterNbit
045.shiftRegister
045.shiftRegister
046.ringcounter
046.ringcounter
047.Debouncepushbutton
047.Debouncepushbutton
048.ClockPulse
048.ClockPulse
049.3bitCounter
049.3bitCounter
050.Nbit counter
050.Nbit counter
053.PWMsignal
053.PWMsignal
.gitignore
.gitignore
readme.md
readme.md
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